Design Engineer

Job Description:

·        ASIC Architecture Design

·        Verilog RTL Design

·        Verilog Simulation / Verification(Conventional, Assertion Based, Formal)

·        RTL Synthesis, Equivalence Checking, Static Timing Analysis

·        Design Debug and Validation

·        Design Documentation

·        Knowledge of Fibre Channel, Ethernet protocol will be considered plus

·        BS or MS or equivalent degree in Electrical Engineering, Computer Engineering or related discipline with 10 years of experience

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